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FUJITSU SEMICONDUCTOR DATA SHEET
Revision 1.5
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89490 Series
MB89497/498/F499/PV490
DESCRIPTION
The MB89490 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit single-chip microcontrollers.
*: F2MC stands for FUJITSU Flexible Microcontroller.
FEATURES
PR
* Package used QFP package for MB89F499, MB89497,MB89498 MQFP package for MB89PV490 * High speed operating capability at low voltage * Minimum execution time: 0.32 s/12.5MHz
EL
IM
IN
The MB89490 series is designed suitable for compact disc/cassette tape/radio receiver controller as well as in a wide range of applications for consumer product.
AR Y
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21-bit timebase timer, watch prescaler, PWM timer, 8/16-bit timer/counter, remote receiver control, LCD controller/driver, external interrupt 0 (edge), external interrupt 1 (level), 10-bit A/D converter, UART/SIO, SIO, I2C and watchdog timer reset.
(Continued)
PACKAGE
100-pin Plastic QFP
100-pin Ceramic MQFP
(FPT-100P-M06)
(FTP-100P-M06)
(MQP-100C-P01)
1
MB89490 Series
(Continued) * F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
Instruction set optimized for controllers
* Clock Embedded PLL clock multiplication circuit for sub-clock Operating clock (PLL for sub-clock) can be selected four times of the sub-clock oscillation * Six timers PWM timer x 2 8/16-bit timer/counter x 2 21-bit timebase timer Watch prescaler * External interrupt Edge detection (selectable edge) : 8 channels Low level interrupt (wake-up function) : 8 channels * 10-bit A/D converter (8 channels) 10-bit successive approximation type * UART/SIO Synchronous/asynchronous data transfer capability * SIO Synchronous data transfer capability * LCD controller/driver Max. 32 segments output x 4 commons * I2C interface circuit * Remote receiver circuit * Low-power consumption mode Stop mode (oscillation stops so as to minimize the current consumption.) Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.) Watch mode (everything except the watch prescaler stops so as to reduce the power comsumption to an extremely low level.) Sub-clock mode * Watchdog timer reset * I/O ports: max. 66channels
PRODUCT LINEUP
Part number Parameter Classification ROM size RAM size MB89497 MB89498 MB89F499 FLASH MB89PV490 Piggy-back
Mass production products (mask ROM product)
32K x 8-bit 48K x 8-bit 60K x 8-bit (internal FLASH) 60K x 8-bit (external ROM)*1 (internal ROM) (internal ROM) 1K x 8-bit 2K x 8-bit 2K x 8-bit 2K x 8-bit
*1 : Use MBM27C512 as the external ROM.
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MB89490 Series
Part number Parameter CPU functions MB89497 MB89498 MB89F499 MB89PV490 : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.32 s/12.5 MHz : 2.88 s/12.5 MHz : 56 pins : 2 pins : 8 pins : 66 pins
Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time I/O ports (CMOS) Input ports (CMOS) N-channel open drain I/O ports Total
Ports
21-bit timebase timer Watchdog timer PWM timer 0,1
Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz Reset period (167.8 ms to 335.5 ms) at 12.5 MHz. 8-bit reload timer operation (supports square wave output, operating clock period: 1, 8, 16, 64 tinst,) 8-bit resolution PWM operation Can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each with its own independent operating clock cycle), or as one 16-bit timer/counter In timer 00 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capability Can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each with its own independent operating clock cycle), or as one 16-bit timer/counter In timer 10 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capability 8 independent channels (selectable edge, interrupt vector, request flag) 8 channels (low level interrupt) 10-bit resolution x 8 channels A/D conversion function (conversion time: 38 tinst ) Supports repeated activation by internal clock : 4 (max.) : 32 (max.) :3 : 32 x 4 bits
8/16-bit timer/ counter 00, 01
8/16-bit timer/ counter 10, 11 External interrupt 0 (edge) External interrupt 1 (level) A/D converter
Common output LCD controller/driver Segment output Bias power supply pins LCD display RAM size UART/SIO SIO Synchronous/asynchronous data transfer capability (Max. baud rate: 97.656 Kbps at 12.5 MHz) (7 and 8 bits with parity bit; 8 and 9 bits without parity bit)
8-bit serial I/O with LSB first/MSB first selectability One clock selectable from four operation clock (one external shift clock, three internal shift clock: 0.64s, 2.56s, 10.24s at 12.5MHz) 1 channel Use a 2-wire protocol to communicate with other device Selectable maximum noise width removal Reversible input polarity Sleep mode, stop mode, watch mode, sub-clock mode CMOS 2.2V ~ 3.6V 2.7V ~ 3.6V 2.7V ~ 3.6V
I2C*1 Remote receiver Standby mode Process Operating voltage
*1 : I2C is complied to Philips I2C specification.
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MB89490 Series
PACKAGE AND CORRESPONDING PRODUCTS
Part number MB89497/498 Package FPT-100P-M06 MQP-100C-P01 O : Availabe X : Not available O X O X X O MB89F499 MB89PV490
DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following point: * The stack area is set at the upper limit of the RAM.
2. Current Consumption
* For the MB89PV490 the current consumed by the EPROM mounted in the piggy-back socket is needed to be included. * When operating at low speed, the current consumed by the FLASH product is greater than that for the mask ROM product. However, the current consumption is roughly the same in sleep and stop mode. * For more information, see " Electrical Characteristics."
3. Oscillation Stabilization Time after Power-on Reset
* For MB89PV490 and MB89F499, the power-on stabilization time cannot be selected. * For MB89497 and MB89498, the power-on stabilization time can be selected. * For more information, please refer to " Mask Option".
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MB89490 Series
PIN ASSIGNMENT
(TOP VIEW)
Vcc *P00 *P01 *P02 *P03 *P04 *P05 *P06 *P07 P10/INT00 P11/INT01 P12/INT02 P13/INT03 P14/INT04 P15/INT05 P16/INT06 P17/INT07 P20/TO0 P21/RMC P22/EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P50/SI0 P51/SO0 P52/SCK0 AVR AVcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Vss X0 X1 MOD0 RST P84 P83 P82/SCK1 P81/SO1 P80/SI1 P77/SEG31 P76/SEG30 P75/SEG29 P74/SEG28 P73/SEG27 P72/SEG26 P71/SEG25 P70/SEG24 P67/SEG23 P66/SEG22
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P65/SEG21 P64/SEG20 P63/SEG19 P62/SEG18 P61/SEG17 P60/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 P54/COM3 P53/COM2 COM1 COM0 V1 V2 V3 Vcc
* High current pins
(FPT-100P-M06)
AVss P30/AN0/INT10 P31/AN1/INT11 P32/AN2/INT12 P33/AN3/INT13 P34/AN4/INT14 P35/AN5/INT15 P36/AN6/INT16 P37/AN7/INT17 *P40 *P41 *P42 *P43 *P44 *P45 *P46/SCL *P47/SDA X1A X0A Vss
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MB89490 Series
(TOP VIEW)
Vss X0 X1 MOD0 RST P84 P83 P82/SCK1 P81/SO1 P80/SI1 P77/SEG31 P76/SEG30 P75/SEG29 P74/SEG28 P73/SEG27 P72/SEG26 P71/SEG25 P70/SEG24 P67/SEG23 P66/SEG22 Vcc *P00 *P01 *P02 *P03 *P04 *P05 *P06 *P07 P10/INT00 P11/INT01 P12/INT02 P13/INT03 P14/INT04 P15/INT05 P16/INT06 P17/INT07 P20/TO0 P21/RMC P22/EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P50/SI0 P51/SO0 P52/SCK0 AVR AVcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
121 122 123 124 125 126 127 128 129
113 112 111 110 109 108 107 106 105
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P65/SEG21 P64/SEG20 P63/SEG19 P62/SEG18 P61/SEG17 P60/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 P54/COM3 P53/COM2 COM1 COM0 V1 V2 V3 Vcc
* High current pins
(MQP-100C-P01)
Pin assignment on package top (MB89PV490 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 101 102 103 104 105 106 107 108 N.C. A15 A12 A7 A6 A5 A4 A3 109 110 111 112 113 114 115 116 A2 A1 A0 N.C. O1 O2 O3 VSS 117 118 119 120 121 122 123 124 N.C. O4 O5 O6 O7 O8 CE A10 125 126 127 128 129 130 131 132 OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: As connected internally, do not use.
6
AVss P30/AN0/INT10 P31/AN1/INT11 P32/AN2/INT12 P33/AN3/INT13 P34/AN4/INT14 P35/AN5/INT15 P36/AN6/INT16 P37/AN7/INT17 *P40 *P41 *P42 *P43 *P44 *P45 *P46/SCL *P47/SDA X1A X0A Vss
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
130 131 132 101 102 103 104
120 119 118 117 116 115 114
MB89490 Series
PIN DESCRIPTION
Pin number MQFP*1/QFP*2 99 98 49 48 97 95, 94 I/O circuit type
Pin name X0
Function
A X1 X0A A X1A MOD0 P84,P83 B J
Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. Connection pins for a crystal or other oscillator. An external clock can be connected to X0A. In this case, leave X1A open. Input pin for setting the memory access mode. Connect directly to VSS. General-purpose CMOS Input port. Reset I/O pin. The pin is an N-ch open-drain type with pull-up resistor and a hysteresis input. The pin outputs an "L" level when an internal reset request is present. Inputting an "L" level initializes internal circuits. General-purpose CMOS I/O port. General-purpose CMOS I/O port. The pin is shared with external interrupt 0 input. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 00, 01 output. General-purpose CMOS I/O port. The pin is shared with remote receiver input. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 00, 01 input. General-purpose CMOS I/O port. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 10, 11 output. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 10,11 input. General-purpose CMOS I/O port. The pin is shared with PWM0 output. General-purpose CMOS I/O port. The pin is shared with PWM1 output. General-purpose CMOS I/O port. The pin is shared with external interrupt 1 input and A/D converter input. General-purpose N-ch open-drain I/O port. General-purpose N-ch open-drain I/O port. The pin is shared with I2C clock I/O. General-purpose N-ch open-drain I/O port. The pin is shared with I2C data I/O. General-purpose CMOS I/O port. The pin is shared with SIO data input. General-purpose CMOS I/O port. The pin is shared with SIO data output. General-purpose CMOS I/O port. The pin is shared with SIO clock I/O.
96
RST
C
2~9 10~17
P00 ~ P07 P10/INT00 ~ P17/INT07 P20/TO0 P21/RMC P22/EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P30/AN0/INT10 ~ P37/AN7/INT17 P40~P45 P46/SCL P47/SDA P50/SI0 P51/SO0 P52/SCK0
D E
18 19 20 21 22 23 24 25
F E E F F E F F
32 ~ 39 40 ~ 45 46 47 26 27 28
G H H H E F E
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MB89490 Series
(Continued)
Pin number MQFP*1/QFP*2 57 58 Pin name I/O circuit type F/I F/I Function General-purpose CMOS I/O port. The pin is shared with the LCD common output. General-purpose CMOS I/O port. The pin is shared with the LCD common output. General-purpose CMOS I/O port. The pin is shared with LCD segment output. General-purpose CMOS I/O port. The pin is shared with LCD segment output. General-purpose CMOS I/O port. The pin is shared with UART/SIO data input. General-purpose CMOS I/O port. The pin is shared with UART/SIO data output. General-purpose CMOS I/O port. The pin is shared with UART/SIO clock I/O. LCD segment output-only pin. LCD common output-only pin. LCD driving power supply pin. Power supply pin. Power supply pin (GND). A/D converter power supply pin. A/D converter reference voltage input pin. A/D converter power supply pin. Use at the same voltage level as VSS.
P53/COM2 P54/COM3 P60/SEG16 ~ P67/SEG23 P70/SEG24 ~ P77/SEG31 P80/SI1 P81/SO1 P82/SCK1 SEG0 ~ SEG15 COM0 ~ COM1 V1 to V3 VCC VSS AVCC AVR AVSS
75 ~ 82
F/I
83 ~ 90
F/I
91 92 93 59 ~ 74 55 ~ 56 54, 53, 52 1,51 50,100 30 29 31 *1: MQP-100C-P01 *2: FPT-100P-M06
E F E I I -- -- -- -- -- --
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MB89490 Series
* External EPROM Socket (MB89PV490 only)
Pin number MQFP*1 102 131 130 103 127 124 128 129 104 105 106 107 108 109 110 111 122 121 120 119 118 115 114 113 101 112 117 126 116 123 125 132 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O8 O7 O6 O5 O4 O3 O2 O1 Pin name I/O Function
O
Address output pins.
I
Data input pins.
N.C.
--
Internally connected pins. Always leave open.
VSS CE OE VCC
O O O O
Power supply pin (GND). Chip enable pin for the EPROM. Outputs "H" in standby mode. Output enable pin for the EPROM. Always outputs "L". Power supply pin for the EPROM.
*1: MQP-100C-P01
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MB89490 Series
I/O CIRCUIT TYPE
Circuit Class
X1 (X1A) N-ch P-ch X0 (X0A) P-ch N-ch N-ch
Circuit
Remarks
A
* Main/Sub-clock circuit
Stop mode control signal
B
R
* Hysteresis input (CMOS input in MB89F499) * The pull-down resistor (not available in MB89F499) Approx. 50k
R P-ch
C
N-ch
* The pull-up resistor (P-channel) Approx. 50 k * Hysteresis input
R P-ch P-ch
pull-up resistor register
D
N-ch
* * * *
port
CMOS output IOH=-4mA, IOL=12mA CMOS input Selectable pull-up resistor Approx. 50 k
R P-ch P-ch
pull-up resistor register
E
N-ch
* * * * *
port resource
CMOS output IOH=-2mA, IOL=4mA CMOS port input Hysteresis resource input Selectable pull-up resistor Approx. 50 k
(Continued) 10
MB89490 Series
(Continued)
R P-ch P-ch pull-up resistor register
F
N-ch
* * * *
port
CMOS output IOH=-2mA, IOL=4mA CMOS input Selectable pull-up resistor Approx. 50 k
R P-ch P-ch
pull-up resistor register
G
N-ch
port resource analog
CMOS output IOH=-2mA, IOL=4mA CMOS port input Automotive (VIH=0.85Vcc, VIL=0.5Vcc) resource input * Analog input * Selectable pull-up resistor Approx. 50 k
* * * *
H
N-ch
port / resource
* * * * *
N-ch open-drain output IOL=15mA CMOS port input CMOS resource input 5V tolerance
P-ch N-ch
I
P-ch N-ch
* LCD segment output
J
* CMOS input
11
MB89490 Series
HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in " Electrical Characteristics" is applied between VCC and VSS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR), and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
7. Treatment of Unused dedicated LCD pins
When dedicated LCD pins are not in use, keep them open.
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MB89490 Series
PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F499
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
* 60 K byte x 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors) * Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200) * Includes an erase pause and restart function * Data polling and toggle bit for detection of program/erase completion * Detection of program/erase completion via CPU interrupt * Compatible with JEDEC-standard commands * Sector Protection (sectors can be combined in any combination) * No. of program/erase cycles : 10,000 (Min) *: Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory.
4. Flash Memory Register
* Control status register (FMCS)
Address 007AH Bit 7 INTE Bit 6 RDYINT Bit 5 WE Bit 4 RDY Bit 3 Bit 2 Bit 1 Bit 0 Reserved Initial value 000X00-0B
Reserved Reserved
-- --
R/W
R/W
R/W
R
R/W
R/W
R/W
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both during CPU access a flash memory programming. * Sector configuration of flash memory Flash Memory 16 K bytes 8 K bytes 8 K bytes 28 K bytes CPU Address FFFFH to C000H BFFFH to A000H 9FFFH to 8000H 7FFFH to 1000H Programmer Address* 1FFFFH to 1C000H 1BFFFH to 1A000H 19FFFH to 18000H 17FFFH to 11000H
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MB89490 Series
* : Programmer address The programmer address is the address to be used instead of the CPU address when programming data from a parallel flash memory programmer. Use the programmer address on programming or erasing using a general purpose parallel programmer.
6. ROM Programmer Adaptor and Recommended ROM Programmers
Adaptor Part No. Sun Hayato Co. Ltd. MB89F499PF FPT-100P-M06 TBD Recommended Programmer Manufacturer and Model Ando Denki Co. Ltd. AF9708 (ver 1.60 or later) AF9709 (ver 1.60 or later)
Part number
Package
* Enquiries Sunhayato Co. Ltd. : FAX +81-3-5396-9106 Ando Denki Co. Ltd. : TEL +81-44-549-7300
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MB89490 Series
PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403
3. Memory Space
Memory space in each mode is shown in the diagram below.
Address 0000H
Normal operating mode I/O
Corresponding addresses on the EPROM programmer
0080H RAM 0880H 1000H Not available 1000H
PROM 60KB
EPROM 60KB
FFFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 1000H to FFFFH. (3) Program to 1000H to FFFFH with the EPROM programmer.
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MB89490 Series
Block Diagram
X0 X1
Main clock oscillator Clock controller
21-bit timebase timer
AVcc AVss AVR
X0A X1A
Sub-clock oscillator (PLL x 1,2,4) Reset circuit (Watchdog timer) Watch prescaler CMOS I/O port
8-bit PWM timer 0
10-bit A/D converter
8
RST
CMOS I/O port
8
Port 3
8
P37/AN7/INT17 to P30/AN0/INT10
External interrupt 1 (level)
P23 P26/PWM0
I2C Internal data bus N-ch open-drain I/O port CMOS I/O port
Port 2
Port 4*1
P47/SDA P46/SCL 6 P45 to P40 P84 P83
P27/PWM1 P21/RMC P22/EC0 P20/TO0 P25/EC1 P24/TO1 P17/INT07 to P10/INT00 8
8-bit PWM timer 1 Remote receiver
8/16-bit timer/counter 00,01 8/16-bit timer/counter 10,11
8
Port 8
UART/SIO
P82/SCK1 P81/SO1 P80/SI1 P52/SCK0 P51/SO0 P50/SI0
SIO CMOS I/O port
2
Port 1
External interrupt 0 (edge)
CMOS I/O port
Port 5
2
P54/COM3 to P53/COM2
P07 to P00
8
Port 0*1
CMOS I/O port
LCD controller/driver
16 SEG0 t0 SEG15 2 COM0 to COM1
RAM (1K bytes / 2K bytes) F2MC-8L CPU
32 x 4-bit display RAM (16 bytes)
16
3 V1 to V3
Port 6, 7
8 8
P67/SEG23 to P60/SEG16 P77/SEG31 to P70/SEG24
ROM (32K bytes / 48K bytes) Other pins Vcc x 2, Vss x 2, MOD0 CMOS I/O port
*1: High current I/O port.
16
MB89490 Series
CPU CORE
1. Memory Space
The microcontrollers of the MB89490 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89490 series is structured as illustrated below.
Memory Space
MB89497 0000H I/O 0080H RAM 0100H 0200H 0480H
Generalpurpose registers
MB89498 0000H I/O 0080H RAM 0100H
Generalpurpose
MB89F499 0000H I/O 0080H RAM 0100H
Generalpurpose
MB89PV490 0000H I/O 0080H RAM 0100H
Generalpurpose
0200H registers 0880H
0200H registers 0880H Vacant 1000H
0200H registers 0880H Vacant 1000H
Vacant
Vacant FLASH (60K) 4000H External ROM (60K)
8000H FFC0H FFFFH
ROM
FFC0H FFFFH
ROM
FFC0H FFFFH
FFC0H FFFFH
Vector table (reset, interrupt, vector call instruction)
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MB89490 Series
2. Registers
The F 2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions. A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for performing arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification. A 16-bit pointer for indicating a memory address. A 16-bit register for indicating a stack area. A 16-bit register for storing a register pointer, a condition code.
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
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MB89490 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear to "0" otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to "1". Interrupt is prohibited when the flag is set to "0". Clear to "0" when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt Priority High
N-flag: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Clear to "0" otherwise. Z-flag: V-flag: Set to "1" when an arithmetic operation results in "0". Clear to "0" otherwise. Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Clear to "0" if the overflow does not occur.
C-flag: Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
19
MB89490 Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB89490 series. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
20
MB89490 Series
I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H DDR2 SYCC STBC WDTC TBTC WPCR PDR3 DDR3 RSFR PDR4 PDR5 DDR5 PDR6 DDR6 PDR7 DDR7 PDR8 DDR8 EIC0 EIC1 EIC2 EIC3 EIE1 EIF1 SMR SDR T01CR T00CR T01DR T00DR T11CR T10CR Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register (Reserved) Port 2 data direction register System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Reset flag register Port 4 data register Port 5 data register Port 5 data direction register Port 6 data register Port 6 data direction register Port 7 data register Port 7 data direction register Port 8 data register Port 8 data direction register External interrupt 0 control register 0 External interrupt 0 control register 1 External interrupt 0 control register 2 External interrupt 0 control register 3 External interrupt 1 enable register External interrupt 1 flag register Serial mode register Serial data register Timer 01 control register Timer 00 control register Timer 01 data register Timer 00 data register Timer 11 control register Timer 10 control register R/W R/W R/W W* R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B X-1MM100B 00010XXXB 0---XXXXB 00---000B 00--0000B XXXXXXXXB 00000000B XXXX----B 11111111B ---XXXXXB ---00000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B ---XXXXXB ---00000B 00000000B 00000000B 00000000B 00000000B 00000000B -------0B 00000000B XXXXXXXXB 000000X0B 000000X0B XXXXXXXXB XXXXXXXXB 000000X0B 000000X0B (Continued) 21 Read/Write R/W W* R/W W* R/W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B 00000000B
MB89490 Series
(Continued) Address 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH to 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH to 5DH 5EH 5FH 60H to 6FH 70H 71H LOCR LCD VRAM PURC0 PURC1 RMN RMC RMS RMD RMCD0 RMCD1 RMCD2 RMCD3 RMCD4 RMCD5 RMCI Register name T11DR T10DR ADER ADC0 ADC1 ADDH ADDL CNTR0 COMR0 SMC0 SMC1 SSD SIDR/SODR SRC CNTR1 COMR1 IBSR IBCR ICCR IADR IDAR PLLCR Register description Timer 11 data register Timer 10 data register A/D input enable register A/D control register 0 A/D control register 1 A/D data register (Upper byte) A/D data register (Lower byte) PWM 0 timer control register PWM 0 timer compare register UART/SIO serial mode control register UART/SIO serial mode control register UART/SIO serial status/data register UART/SIO serial data register UART/SIO serial rate control register PWM 1 timer control register PWM 1 timer compare register I C bus status register I2C bus control register I2C clock control register I C address register I C data register Sub PLL control register (Reserved) Remote control counter register Remote control control register Remote control status register Remote control FIFO data register Remote control compare register 0 Remote control compare register 1 Remote control compare register 2 Remote control compare register 3 Remote control compare register 4 Remote control compare register 5 Remote interrupt register (Reserved) LCD controller output control register LCD controller control register LCD data RAM Port 0 pull up resistor control register Port 1 pull up resistor control register R/W R/W R/W R/W R/W -0000000B 00010000B XXXXXXXXB 11111111B 11111111B (Continued) 22 R R/W R/W R R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB 00000000B 0X000001B X----XXXB 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B -110-000B
2 2 2
Read/Write R/W R/W R/W R/W R/W R R R/W W* R/W R/W R/W R/W R/W R/W W* R R/W R/W R/W R/W R/W
Initial value XXXXXXXXB XXXXXXXXB 11111111B -00000X0B -0000001B ------XXB XXXXXXXXB 0-000000B XXXXXXXXB 00000000B 00000000B 00001---B XXXXXXXXB XXXXXXXXB 0-000000B XXXXXXXXB 00000000B 00000000B 000XXXXXB XXXXXXXXB XXXXXXXXB ----0000B
MB89490 Series
(Continued) Address 72H 73H 74H 75H 76H 77H 78H to 79H 7AH 7BH 7CH 7DH 7EH 7FH FMCS ILR1 ILR2 ILR3 ILR4 Register name PURC2 PURC3 PURC5 PURC6 PURC7 PURC8 Register description Port 2 pull up resistor control register Port 3 pull up resistor control register Port 5 pull up resistor control register Port 6 pull up resistor control register Port 7 pull up resistor control register Port 8 pull up resistor control register (Reserved) Flash memory control status registger Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 (Reserved) R/W W* W* W* W* 000X00-0B 11111111B 11111111B 11111111B 11111111B Read/Write R/W R/W R/W R/W R/W R/W Initial value 11111111B 11111111B ---11111B 11111111B 11111111B -----111B
* Bit manipulation instruction cannot be used. Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". X: The initial value of this bit is undefined. - : Unused bit. M: The initial value of this bit is determined by mask option.
23
MB89490 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC AVR LCD power supply voltage V1 to V3 Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Input voltage VI VSS - 0.3 VSS - 0.3 Output voltage VO VSS - 0.3 -40 -55 Max. VSS + 4.0 VSS + 4.0 VCC VCC + 0.3 VSS + 6.0 VSS + 5.5 VCC + 0.3 15 4 100 40 -15 -4 -50 -20 300 +85 +150 Unit V V V V V V V mA mA mA mA mA mA mA mA mW C C Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) Average value (operating current x operating rate) other than P40~P47 P40~P47 in MB89PV490, MB89497/498 P40~P47 in MB89F499 Remarks AVCC must be equal to VCC
Power supply voltage
"L" level maximum output current IOL "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature IOLAV IOL IOLAV
IOH IOHAV IOH IOHAV
PD TA Tstg
Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
24
a a a a
MB89490 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 2.7* VCC AVCC 2.2* 1.5 AVR LCD power supply voltage Operating temperature V1 to V3 TA 2.7 Vss -40 Max. 3.6 3.6 3.6 3.6 Vcc +85 Unit V V V V V C Remarks Operation assurance range Operation assurance range Retains the RAM state in stop mode MB89PV490, MB89F499 MB89497, MB89498
Power supply voltage
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2 and "5. A/D Converter Electrical Characteristics."
Operating voltage (V) 3.6 3.0 2.7 2.2 2.0 Analog accuracy assurance range : Vcc = AVcc = 2.7V~3.6V
Main clock operating freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 0.4 11.0 12.0 12.5 0.36 0.33 0.32 Min execution time (inst. cycle) (s)
Note : The shaded area is not assured for MB89F499
Figure 1
Operating Voltage vs. Main Clock Operating Frequency (MB89F499/497/498)
25
MB89490 Series
Operating voltage (V)
3.6 3.5 3.0 2.7
Analog accuracy assurance range : Vcc = AVcc = 2.7V~3.6V
Main clock operating Freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 0.4 11.0 12.0 12.5 0.36 0.33 0.32 Min execution time (inst. cycle) (s)
Figure 2
Operating Voltage vs. Main Clock Operating Frequency (MB89PV490)
Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear.
26
MB89490 Series
3. DC Characteristics
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Symbol Pin P00 ~ P07, P10 ~ P17, P20 ~ P27, P30 ~ P37, P50 ~ P54, P60 ~ P67, P70 ~ P77, P80 ~ P84, SCL, SDA, MOD1, MOD2 P40 ~ P47 RST, MOD0, EC0, EC1, SCK0, SI0, SCK1, SI1, RMC, INT00 ~ INT07 INT10 ~ INT17 P00 ~ P07, P10 ~ P17, P20 ~ P27, P30 ~ P37, P40 ~ P47, P50 ~ P54, P60 ~ P67, P70 ~ P77, P80 ~ P84, SCL, SDA, MOD1, MOD2 RST, MOD0, EC0, EC1, SCK0, SI0, SCK1, SI1, RMC, INT00 ~ INT07 INT10 ~ INT17 Condition Value Min. Typ. Max. Unit Remarks
--
0.7 VCC
--
VCC + 0.3
V
VIH "H" level input voltage
-- --
0.7 VCC 0.7 VCC
-- --
VSS + 6.0 VSS + 5.5
V V
MB89PV490, MB89497/498 MB89F499
VIHS
--
0.8 VCC
--
VCC + 0.3
V
VIHA
--
0.85 VCC
--
VCC + 0.3
V
VIL "L" level input voltage
--
VSS - 0.3
--
0.3 VCC
V
VILS
--
VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3
--
0.2 VCC
V
VILA Open-drain output pin application voltage
-- --
-- -- --
0.5 VCC VSS + 6.0 VSS + 5.5
V V V MB89PV490, MB89497/498 MB89F499
VD
P40 ~ P47 -- P10 P20 P30 P50 P60 P70 P80 ~ P17, ~ P27, ~ P37, ~ P54, ~ P67, ~ P77, ~ P82
"H" level VOH output voltage
IOH = -2.0 mA
2.2
--
--
V
P00 ~ P07
IOH = -4.0 mA
2.2
--
--
V
(Continued)
27
MB89490 Series
(Continued)
Parameter
Symbol P10 ~ P20 ~ P30 ~ P50 ~ P60 ~ P70 ~ P80 ~
Pin P17, P27, P37, P54, P67, P77, P82, RST
Condition
Value Min. Typ. Max.
Unit
Remarks
IOL = 4.0 mA
--
--
0.4
V
"L" level VOL output voltage
P00 ~ P07 P40 ~ P47 P00 ~ P10 ~ P20 ~ P30 ~ P40 ~ P50 ~ P60 ~ P70 ~ P80 ~ P07, P17, P27, P37, P47, P54, P67, P77, P84
IOL = 12.0 mA IOL = 15.0 mA
-- --
-- --
0.4 0.4
V V
Input leakage current
ILI
0.45 V < VI < VCC
-5
--
+5
A
Without
pull-up resistor
Open-drain output leakage ILOD current Pull-down resistance RDOWN
P40 ~ P47
0.0 V < VI < VCC
-5 25
--
+5 100
A
k Except MB89F499 When pull-up resistor is selected (except RST)
MOD0 P00 ~ P10 ~ P20 ~ P30 ~ P50 ~ P60 ~ P70 ~ P80 ~ RST P07, P17, P27, P37, P54, P67, P77, P82,
VI = VCC
50
Pull-up resistance
RPULL
VI = 0.0 V
25
50
100
k
Common output impedance Segment output impedance
RVCOM
COM0 to COM3
V1 to V3 = +3.0 V
--
--
2.5
k
RVSEG
SEG0 to SEG31 -- V1 to V3, COM0 to COM3, SEG0 to SEG31
V1 to V3 = +3.0 V Between VCC and VSS
-- 300
-- 500
15 750
k k
LCD divided RLCD resistance LCD controller/ driver leakage current
ILCDL
--
-1
--
+1
A
(Continued)
28
MB89490 Series
(Continued)
Parameter Symbol Pin Condition FCH = 10 MHz tinst = 0.4 s Main clock run mode FCH = 10 MHz tinst = 6.4 s Main clock run mode FCH = 10 MHz tinst = 0.4 s Main clock sleep mode FCH = 10 MHz tinst = 6.4 s Main clock sleep mode FCL = 32.768 kHz Sub-clock mode TA = +250C FCL = 32.768 kHz Sub-clock mode TA = +250C sub PLL x 4 FCL = 32.768 kHz Sub-clock sleep mode TA = +250C FCL = 32.768 kHz Watch mode Main clock stop mode TA = +250C TA = +250C Sub-clock stop mode AVcc = 3.0 V, TA = +25 C AVcc TA = +25 C Other than VCC, VSS, AVCC, f = 1 MHz AVSS, AVR
0 0
Value Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. 3.5 6.0 0.4 1.5 1.2 2.0 0.4 1.0 22.0 35.0 120.0 150.0 7.0 15.0 1.0 5.0 0.8 1.0 1.0 0.8 10.0 Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 3.0 4.0 --
Unit mA mA mA mA mA mA mA mA
Remarks MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 MB89PV490, MB89497/498 MB89F499 A/D converting
ICC1
ICC2
ICCS1
ICCS2
ICCL Power supply current ICCLPLL
A A A A A A A A A A
mA
VCC
ICCLS
ICCT
ICCH IA IAH Input capacitance CIN
A
pF
A/D stop
29
MB89490 Series
4. AC Characteristics
(1) Reset Timing (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min. Max. -- 48 tHCYL -- ns
Parameter RST "L" pulse width
Symbol tZLZH
Note: tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin. The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.
tZLZH RST
0.2 VCC
0.2 VCC
(2) Power-on Reset (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition Value Min. -- 1 Max. 50 -- Unit ms ms Due to repeated operations Remarks
--
Note: Make sure that power supply rises within the selected oscillation stabilization time. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 1.5 V 0.2 V
tOFF
VCC
0.2 V
0.2 V
30
MB89490 Series
(3) Clock Timing (AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter Clock frequency Symbol FCH FCL tHCYL tLCYL PWH PWL PWHL PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A Value Min. 1 -- 80 13.3 20 -- -- Typ. -- 32.768 -- 30.5 -- 15.2 -- Max. 12.5 75 1000 -- -- -- 10 Unit MHz kHz ns s ns s ns External clock Remarks
Clock cycle time
Input clock pulse width
Input clock rising/falling time
X0 and X1 Timing and Conditions
tHCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL
Main Clock Conditions
When a crystal or ceramic reasonator is used When an external clock is used
X0
X1 FCH C1 C2
X0
X1 Open
FCH
31
MB89490 Series
Sub-clock Timing and Conditions
tLCYL 0.8 VCC 0.2 VCC PWHL PWLL tCF tCR
X0A
Sub-clock Conditions
When a crystal or ceramic oscillator is used
When an external clock is used
When subclock is not used
X0A FCL
X 1A Rd
X0A
X1A Open FCL
X0A
X1A
Open
C0
C1
(4) Instruction Cycle
Parameter Instruction cycle (minimum execution time)
Symbol
Value 4/FCH, 8/FCH, 16/FCH, 64/FCH
Unit s s
Remarks (4/FCH)tinst = 0.32 s when operating at FCH = 12.5 MHz (2/FCL)tinst = 61.036 s when operating at FCL = 32.768 kHz
tinst 2/FCL, 1/2FCL
32
MB89490 Series
PLL operation guarantee range (subPLL x 4)
Relationship between internal operating clock frequency and power supply voltage
Operating voltage (V)
subPLL operating guarantee range
3.6 3.0 2.7 2.5 2.0 Internal operating clock freq. (kHz) 131.072 15.625
Not assured for MB89F499, MB89PV490.
300 6.67 Min execution time (inst. cycle) (s)
Relationship between subclock oscillating frequency and instruction cycle when subPLL is enabled Instruction cylcle, Tinst (min. exec. time) (us) 15.625
Multipliedby-4
6.67
75 Oscillation clock FCL (kHz)
32.768
33
MB89490 Series
(5) Serial I/O Timing (AVCC = VCC = 3.0 V, AVSS = VSS= 0.0 V, TA = -40C to +85C) Value Pin Condition Unit Min. Max. SCK0, SCK1 SCK0, SCK1, SO0, SO1 SI0, SI1, SCK0, SCK1 SCK0, SCK1, SI0, SI1 SCK0, SCK1 SCK0, SCK1, SO0, SO1 SI0, SI1, SCK0, SCK1 SCK0, SCK1, SI0, SI1 External shift clock mode Internal shift clock mode 2 tinst* -200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* -- 200 -- -- -- -- 200 -- -- s ns s s s s ns s s
Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
* : For information on tinst, see "(4) Instruction Cycle." Internal Clock Operation
tSCYC
SCK0, SCK1
2.4 V 0.8 V
tSLOV
0.8 V
SO0, SO1
2.4 V 0.8 V
tIVSH tSHIX 0.8 VCC 0.2 VCC
0.8 VCC
SI0, SI1
0.2 VCC
External Clock Operation
tSLSH
SCK0, SCK1
tSHSL 0.8 VCC 0.8 VCC
0.2 VCC
tSLOV
0.2 VCC
SO0, SO1
2.4 V 0.8 V
tIVSH 0.8 VCC
SI0, SI1
tSHIX
0.8 VCC 0.2 VCC
0.2 VCC
34
MB89490 Series
(6) I2C Timing (Vcc = 3.0V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min. Max. master 1/4tinst x 1/4tinst*1 x ns mode M x N + 20 M x N - 20 1/4tinst x 1/4tinst x master ns (M*2 x N*3 + 8) + (M x N + 8) - 20 mode 20 1/4tinst x 6 + 40 1/4tinst x 6 + 40 -- -- ns ns
Parameter
Symbol
Pin SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA
Condition
Start condition output tSTA Stop condition output tSTO Start condition detect tSTA Stop condition detect tSTO
Re-start condition 1/4tinst x 1/4tinst x master tSTASU ns output (M x N + 8) - 20 (M x N + 8) + 20 mode Re-start condition -- ns 1/4tinst x 4 + 40 tSTASU detect 1/4tinst x SCL output LOW 1/4tinst x master SCL tLOW ns width M x N - 20 M x N + 20 mode 1/4tinst x 1/4tinst x master SCL output HIGH SCL ns tHIGH (M x N + 8) - 20 (M x N + 8) + 20 mode width SDA 1/4tinst x 4 - 20 1/4tinst x 4 + 20 ns SDA output delay tDO SDA output setup tDOSU SDA 1/4tinst x 4 - 20 -- ns *4 time after interrupt SCL input LOW SCL 1/4tinst x 6 + 40 -- ns tLOW pulse width SCL input HIGH SCL 1/4 tinst x 2 + 40 -- ns tHIGH pulse width SDA input setup time tSU SDA 40 -- ns SDA hold time tHO SDA 0 -- ns *1: For information in tinst, see "(4) Instruction Cycle". *2: M is defined in the ICCR CS4 and CS3 (bit 4 to bit 3). For details, please refer to the H/W manual register explanation. *3: N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) *4: When the interrupt period is grater than SCL "L" width, SDA and SCL output (Standard) value is based on hypothesis when rising time is 0 ns.
Data transmit (master/slave)
tDO tDO
tSU
tHO
tDOSU
SDA
tSTASU tSTA tLOW tHO
ACK
SCL
1
9
Data receive (master/slave)
tSU tHO tDO tDO tDOSU
SDA
tHIGH tLOW
ACK
tSTO
SCL
6
7
8
9
35
MB89490 Series
(7) Peripheral Input Timing (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin Unit Remarks Min. Max.
EC0, EC1, RMC, INT00 ~ INT07, INT10 ~ INT17
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1
Symbol tILIH1 tIHIL1
2 tinst* 2 tinst*
-- --
s s
* : For information on tinst, see "(4) Instruction Cycle."
t IHIL1
t ILIH1
EC0, EC1, RMC, INT00 ~ INT07
0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
t IHIL1
t ILIH1
INT10 to INT17
0.85 VCC 0.5 VCC 0.5 VCC 0.85 VCC
36
MB89490 Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics (AVCC = VCC = 2.7 V ~ 3.6 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current VOT VFST -- IAIN VAIN -- IR IRH AVR AN0 to AN7 -- -- Symbol Pin Value Min. -- -- -- -- Typ. 10 -- -- -- Max. -- 3.0 2.5 1.9 Unit bit LSB LSB LSB mV mV Remarks
AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB AVCC - 3.5 LSB AVCC - 1.5 LSB AVCC - 0.5 LSB -- -- AVSS AVSS + 2.7 -- -- -- -- -- -- 200 -- 38 tinst* 10 AVR AVCC TBD 5
s A
V V
A A
A/D is activated A/D is stopped
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics".
(2) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics. * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. * Total error (unit: LSB) The difference between theoretical and actual conversion values.
37
MB89490 Series
Theoretical I/O characteristics 3FF 3FE 3FD 1.5 LSB VFST 3FF 3FE 3FD
Total error
Actual conversion value
{1 LSB x N + VOT}
Digital output
004 003 002 001 0.5 LSB AVSS Analog input AVCC
Digital output
004 003
VNT Actual conversion value Theoretical value
VOT 1 LSB
002 001 AVSS
AVCC Analog input
1 LSB =
VFST - VOT 1022
(V)
Total error = VNT - {1 LSB x N + 0.5 LSB} 1 LSB
Full-scale transition error
Zero transition error 004 Actual conversion value 003 3FF
Theoretical value
Actual conversion value
Digital output
Digital output
3FE VFST (Actual measurement) Actual conversion value 3FC AVCC
002 Actual conversion value 001
3FD
VOT (Actual measurement) AVSS Analog input
Analog input
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x N + VOT} VFST (Actual measurement) N+1
Differential linearity error
Theoretical value
Actual conversion value
V(N + 1)T
Digital output
Digital output
N
VNT
004 003 002 001 AVSS Analog input Theoretical value
N-1 Actual conversion value
VNT Actual conversion value
N-2 AVCC Analog input
VOT (Actual measurement) AVCC AVSS
Linearity error =
VNT - {1 LSB x N + VOT} 1 LSB
Differential linearity error =
V(N + 1)T - VNT 1 LSB
-1
38
MB89490 Series
(3) Notes on Using A/D Converter * Input impedance of the analog input pins The A/D converter used for the MB89490 series contains a sample and hold circuit as illustrated below to fetch analog input voltage into the sample and hold capacitor for 16 instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 F for the analog input pin. Analog Input Circuit Model
Analog input pin
If the analog input impedance is higher than 10 k, it is recommended to connect an external capacitor of approx. 0.1 F.
Sample hold circuit
Comparator R C
Close for 16 instruction cycles after activating A/D conversion. Analog channel selector
R: analog input equivalent resistance C: analog input equivalent capacitance
MB89F499 2.4 k 52 pF
MB89PV490/MB89497/MB89498 2.4 k 53 pF
39
MB89490 Series
MASK OPTIONS
Part number No. Specifying procedure Selection of oscillation stabilization time (OSC) * The initial value of the oscillation stabilization OSC time for the main clock 1 can be set by 2 3 selecting the values of the WTM1 and WTM0 bit on the right. MB89497 MB89498 MB89F499 MB89PV490
Specify when ordering mask
Setting not possible
Selectable : 210/FCH : 214/FCH : 218/FCH Fixed to oscillation stabilization time of 218/FCH
1
40
MB89490 Series
ORDERING INFORMATION
Part number MB89497PF MB89498PF MB89F499PF MB89PV490CF Package 100-pin Plastic QFP (FPT-100P-M06) 100-pin Ceramic MQFP (MQP-100C-P01) Remarks
41
MB89490 Series
PACKAGE DIMENSIONS
100-pin Plastic QFP FPT-100P-M06
23.900.40(.941.016) 20.000.20(.787.008)
80 51
81
50
0.10(.004) 17.900.40 (.705.016) 14.000.20 (.551.008) INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off)
0.65(.026)
0.320.05 (.013.002)
0.13(.005)
M
"A"
C
2001 FUJITSU LIMITED F100008S-c-4-4
Dimensions in mm (inches)
(Continued)
42
MB89490 Series
(Continued)
100-pin ceramic MQFP MQP-100C-P01
18.70(.736)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 12.35(.486)TYP
+0.40 +.016 -.008
INDEX AREA
1.20 -0.20 .047
0.650.15 (.0256.0060)
0.650.15 (.0256.0060)
1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP
18.85(.742) TYP
1.270.13 (.050.005)
0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP
0.300.08 (.012.003)
0.300.08 (.012.003)
1.20 -0.20 .047 -.008
+0.40 +.016
10.82(.426) 0.150.05 MAX (.006.002)
C
1994 FUJITSU LIMITED M100001SC-1-2
43
MB89490 Series
MEMO
44
MB89490 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/ or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
F0208 FUJITSU LIMITED Printed in Japan 45
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